1. Field of the Invention
The present invention relates to a NAND type nonvolatile memory, and more particularly to a NAND type nonvolatile memory enabling Erase-verify operations while ensuring a larger erase margin.
2. Description of the Related Art
In flash memory and other types of nonvolatile memory having NAND type memory cell structure, FN tunneling (Fowler/Nordheim tunneling)is utilized for injecting electrons into a floating gate in order to program and for draining electrons in order to erase. Energy consumption is therefore lower than with NOR type flash memory. A plurality of memory cell transistors are connected in series in a cell string connected to a bit line, and during a Read operation a Read voltage is applied to the gate of a selected cell transistor, with high voltage being applied to the remaining cell transistors to render them all conducting. Accordingly, as the current flowing through the cell string is relatively low, the power consumed during a Read operation is also low. As there limits to the number of cell transistors that can be provided in a cell string, sector size is smaller than with NOR type nonvolatile memory and the erase unit is smaller size. NAND type nonvolatile memory having the characteristics described hereinabove has enjoyed widespread use in recent years.
FIG. 12 is a sectional view of a memory cell transistor in a typical NAND type flash memory. In FIG. 12 (a) shows the erased state and (b) shows the programmed state. Cell transistor structure comprises a source region S and a drain region D formed on a semiconductor substrate surface, a tunnel oxide film OX formed therebetween, a floating gate FG, and a control gate CG. In the erased state (a) shown in FIG. 12, electrons have been drained from floating gate FG; cell transistor threshold voltage Vt is negative so the function thereof is one of a depletion mode transistor. In the programmed state (b) shown in FIG. 12, on the other hand, electrons have been injected into floating gate FG, and cell transistor threshold voltage Vt is positive so the function thereof is one of an enhancement mode transistor.
FIG. 13 is a figure showing a cell string and a page buffer circuit of a NAND type flash memory. Cell string CS is connected to a bit line BL via a select transistor NSG1 and has serially connected memory cells MC0-MCn. To the opposite side of cell string CS is provided a select transistor NSG2 for connection to an array Vss potential ARVss.
Bit line BL is connected via transistors N10, N11 to sense buffer 100. Sense buffer 100 senses the state of memory cell threshold voltage during Read, Program-verify, and Erase-verify operations, and has a latching function. In the figure, N is an n-channel transistor, and P is a p-channel transistor. Sense buffer 100 has a latching circuit 10.
Transistor N1 is a page buffer select transistor connected to output terminal PBOUT. Transistors P2, P3, N4, N5, and N6 are output CMOS circuits. Transistor P7 is a constant current supply source.
For a Read operation, the word line WL of the selected memory cell is driven to about 0 V while the other word lines WL are driven to about 4 V, whereby the selected memory cell turns on or off depending on the state of the threshold voltage, while all of the unselected cells turn on. Depending on whether the selected memory cell is on or off, node SNS goes to H level or to L level; this state is read via conduction or non-conduction by a sense transistor N8 when a Read pulse is applied to a signal SET for conducting the transistor N9, and is latched by latching circuit 10.
Program-verify and Erase-verify operations are carried out analogously to Read operations. For a Program-verify operation, however, instead of driving the word line of the selected memory cell to 0 V, a positive voltage corresponding to Program-verify level, for example 0.8 V, is applied. For an Erase-verify operation, the word line of the selected memory cell is driven to negative voltage corresponding to Erase-verify level instead of to 0 V. However, as it is impractical in semiconductor devices to generate negative voltage, typical practice is to drive the word line of the selected memory to 0 V and the array Vss potential ARVss to positive voltage, for example 0.6 V, so that the word line potential of the selected memory cell becomes negative equivalently.
FIG. 14A shows a redundant data storage circuit used in a NAND type flash memory. With this circuit, a redundant memory cell RMC for storing a redundant address is interposed between select transistors RSG1, RSG2 and connected to a sense amp 101. The threshold voltage state of redundant memory cell RMC is read to node SNS by transistors P21, N20 and a NAND gate 12 in sense amp 101, and the state of node SNS is sensed by a CMOS inverter comprising transistors P22, N23. As with ordinary memory cells, the redundant memory cell RMC has negative threshold voltage during erase operations and positive threshold voltage during programming operations.
For a Read operation, the word line WL of redundant memory cell RMC is driven to 0 V whereby it turns on or off depending upon the state of the threshold voltage, and the information therein is read to node SNS. During Program-verify operations, the word line WL of redundant memory cell RMC is driven to a positive voltage corresponding to Program-verify level, and information of whether threshold voltage exceeds the Program-verify level is read to node SNS and sensed by the CMOS inverter. During Erase-verify, the word line WL of redundant memory cell RMC is driven to 0 V, the array Vss voltage ARVss is driven to positive voltage, and word line WL is driven to negative voltage equivalently. Examples of voltages for each operation are given in FIG. 14B.
As described hereinabove, NAND type flash memory has a different structure than NOR type flash memory, in which memory cell threshold voltage is positive during programming operations and negative during erase operations. Thus, with NAND type memory, the practice is to control the array Vss voltage ARVss to positive voltage in order to verify that memory cell or redundant cell threshold voltage Vt is negative during Erase-verify operations.
However, the page buffer circuit 100 in FIG. 13 and the circuit design of the sense amp 101 of FIG. 14 have problems pertaining to Erase-verify operations.
With the constitution of page buffer 100 of FIG. 13, at the erase verify operation, with 0 V applied to word line WL0 for the selected memory cell MC0 and with 4 V applied to the other word lines and to select lines SG1, SG2, transistors N10, N11 are rendered conducting. If the threshold voltage of selected memory cell MC0 is sufficiently negative, selected memory cell MC0 becomes conducting and the voltage on node SNS is pulled down, this voltage being sensed by transistor N8 and latched by latching circuit 10.
However, threshold voltage for transistor N8 is typically on the order of 0.8V, depending on the production process. Thus, by conduction by selected memory cell MC0, node SNS must be driven lower than the threshold voltage of transistor N8. In such instances, where, from a reliability standpoint, it is necessary to ensure a larger erase margin with respect to Read operations, array Vss voltage ARVss is increased to about 1 V for example, and gate voltage for selected memory cell MC0 equivalently becomes -1 V. By so doing, in case where the selected memory cell MC0 becomes the negative threshold voltage Vt due to sufficient electron drain from the floating gate during erase operations so that even in the conducting state, the potential on node SNS drops at most to array Vss voltage ARVss (=1 V); at this node potential, transistor N8, whose source is connected to ground potential Vss, cannot be rendered non-conducting, and ultimately the Erase-verify operation cannot be performed. That is, whereas a successful Erase-verify operation requires non-conduction of the sense transistor N8 to not invert the state of latching circuit 10, sense transistor N8 cannot be rendered non-conducting even in an erased state.
The same problem relating to Erase-verify also exists in the case of the redundant data storage circuit of FIG. 14A as well. Like the page buffer circuit 100 of FIG. 13, the sense amp 101 of FIG. 14 has a redundant memory cell RMC connected via select transistor RSG1 and transistor N20 with a p-channel transistor P21 serving as a constant current supply source, and node SNS assumes H level or L level depending on whether redundant memory cell RMC is conducting or non-conducting, with the potential on node SNS being sensed by the CMOS inverter having a sense transistor N23 with the source thereof connected to ground Vss.
In this case as well, since it is necessary to ensure a larger erase margin with respect to Read operations, the array Vss voltage ARVss is increased to about 1 V for example, and gate voltage for redundant memory cell RMC equivalently becomes -1 V at the erase verify operation. By so doing, redundant memory cell RMC becomes the negative threshold voltage Vt due to sufficient electron drain from the floating gate so that even in the conducting state, potential on node SNS drops at most to array Vss voltage ARVss (=1 V). This node SNS potential is higher than the trip level of the CMOS inverter P22, N23, and transistor N23, whose source is connected to ground potential Vss, cannot be rendered non-conducting, so that ultimately the Erase-verify operation cannot be performed.
From the preceding it will be apparent that in circuits wherein a node level between a memory cell and a constant current is presented to the gate of a sense transistor having a grounded source, and verify operations are performed via conduction of this sense transistor, Erase-verify operations thereof will be impaired.